An FPGA-based implementation for repeated square-and-multiply polynomials

This paper presents a novel FPGA based method to implement a repeated squared-and-multiply algorithm in polynomial rings. The repeated square-and-multiply algorithm for exponentiation is discussed and constructed for a general function f(x). From that, an algorithm to apply for f(x)=x
ⁿ
+1 is also constructed and described in this paper. Simulations and implementation results using an FPGA are provided and discussed.