Design of a low power charge pump circuit for phase-locked loops

In this paper, the design of a charge pump circuit suitable for lower power PLL-based frequency synthesizer is presented. The charge pump circuit was designed in 0.18μm CMOS process. The proposed charge pump circuit improves current matching in a wide output voltage range by applying a wide input ranged operational amplifier. The percentage error of current mismatch for the output range from 0.3V to 1.7V is less than ±0.005%. The power consumption of the proposed charge pump circuit is around 0.56mW at a supply voltage of 1.8V.