A 15-ns 4-Mb CMOS SRAM

A 4-Mb SRAM with a 15-ns access time and a uniquely selectable (*4 or *1) bit organization has been developed based on a 0.55- mu m triple-polysilicon double-metal CMOS technology. An input-controlled PMOS-load (ICPL) sense amplifier, Y-controlled bit-line loads (YCLs), and a transfer word driver (TDW) are three key circuits which have been utilized in addition to the 0.55- mu m CMOS technology to achieve the remarkable access time of 15 ns. Bit organization of either *4 or *1 can be selected purely electrically, and does not require any pin connection procedure.<
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