Cleaning after silicon oxide CMP

With the decrease of the device dimensions, back-end layer planarisation by Chemical Mechanical Polishing (CMP) seems now absolutely necessary for technologies down to 0.35 μm. CMP processes induce billions of particles, parasitic metallic contaminations and a damaged layer at the top surface of the dielectrics. It is therefore necessary to add a new powerful cleaning process after each CMP step which was not necessary in the past. We early defined the general concepts of cleanings adapted to back-end steps. We propose here to apply our previous results to the practical case of PECVD TEOS oxide CMP where SiO
₂
slurries are used.