Implementation of PSK and QAM demodulators on FPGA

Communication is possible if the signal from transmitter is demodulated properly in the receiver and the quality of the communication depends on the accuracy of demodulation. In this study, a digital receiver building is developed in order to demodulate variable symbol rate PSK or QAM modulated signal in a nosiy channel under carrier and symbol timing error conditions. According to this purpose a digital demodulator is designed and implemented on a Xilinx Virtex-4SX35 FPGA board. FPGA Design stages and simulation results of developed model are presented in this paper.