Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference

This brief presents an area-efficient low-noise architecture for an analog phase-locked loop (PLL) working off a low frequency reference. The architecture has been demonstrated in a 100-400-MHz PLL implemented for wireless connectivity and broadcast applications. It can easily be extended to gigahertz (GHz) operations. A low reference frequency forces a low loop bandwidth, which requires large loop filter components. The challenge is to keep the area small while meeting the jitter specs. By using a charge-pumpless architecture with a novel windowing function, we were able to stabilize the loop with a large resistor and a moderate capacitor without degrading phase noise due to the large thermal noise from the resistor. This provides substantial advantage for area reduction. The windowing function also improves leakage-induced spurs by 16 dB. The PLL was designed in a 45-nm CMOS all-digital process. It occupies an area of 0.09 mm
²
and draws a total current of 800 μA.