A survey on different keeper design topologies for high speed wide AND-OR domino circuits

In this paper, we analyze and compare different keeper design topologies for lowering the active mode power consumption, increasing the speed, enhancing the noise immunity and reducing the subthreshold leakage energy of domino logic circuits. This work briefly surveys domino keeper techniques for high fan-in domino circuits. We compared the power, delay, process tracking and VDD tracking of different topologies. These topologies have been prototyped in 130nm CMOS technology at 125°C temperature. The simulation results reveal that conditional keeper technique gives the better results in terms of reduction in delay, power consumption whereas Leakage current replica (LCR) based keeper shows superior performance in terms of noise overhead, process variation and V
_DD
tracking as compared to other alternatives keepers. As compare to conventional circuit, conditional keeper gives 55% reduction in delay as well as 15% reduction in power while leakage current replica (LCR) gives 95% reduction in noise overhead and providing capability of process and VDD tracking.