Testing memory modules in SRAM-based configurable FPGAs

This paper studies the issues involved in testing memory modules (configured as LUTs and RAMs) in FPGAs and proposes new algorithms as this scenario is substantially different from traditional memory testing. Test generation for LUTs and RAMs is analyzed and discussed by reducing the number of configurations as primary objective. It is proved that a memory with n inputs and two programmable modes (given by the LUT-mode and the RAM-mode) can be tested using a total of 4n/spl times/2/sup n/ READs and 2n/spl times/2/sup n/ WRITEs in 2n+1 configurations (in practice n/spl Lt/5). The conditions by which constant testability of one-dimensional arrays made of memories in a given mode is possible are presented. Hence, to test n/sub r/ memories with two programmable modes, the number of configurations is given by 3n and the number of tests is 8n/spl times/2/sup n/. The application to Xilinx and Altera FPGAs is presented.