A low-power high storage capacity structure for GaAs MESFET ROM

Gallium Arsenide (GaAs) is used in the design of high speed systems; however, it is difficult or impossible to realize high-capacity ROMs, because of subthreshold currents and an unacceptable power dissipation. This paper describes a new approach which overcomes the above problems and allows the realization of both low-power and high storage capacity ROMs in GaAs. In this technique, called DDM (Divided Decoder Matrix), low-power operation is obtained by powering down the parts which are not situated in the addressing path, while high-storage capability is obtained by limiting the leakage currents in the ROM matrix. In addition, this approach improves the noise margin of the DCFL gate with the increase of the fan-in. As an application of the DDM technique, an 8 Kbit MESFET ROM has been designed with a standard 0.6 /spl mu/m-gate MESFET process. The ROM has a typical access time of 1.2 ns and a power dissipation of 60 mW.