Nonlinear copper behavior of TSV and the cracking risks during BEoL-built-up for 3D-IC-integration

The application of copper-TSVs for 3D-IC-integration generates novel challenges for reliability analysis and prediction, i.e. to master multiple failure criteria for combined loading including residual stresses, interface delamination, cracking and fatigue. So, the thermal expansion mismatch between copper and silicon yields to stress situation in silicon surrounding the TSVs which is influencing the electron mobility and as a result the transient behavior of transistors. Furthermore, pumping and protrusion of copper is a challenge for Back-end of Line (BEoL) layers of advanced CMOS technologies already during manufacturing. These effects depend highly on the temperature dependent elastic-plastic behavior of TSV-copper and the residual stresses determined by the electro deposition chemistry and annealing conditions. That's why the authors pushed combined simulative/experimental approaches to extract the YOUNG's-modulus, initial yield stress and hardening coefficients from nanoIndentation experiments in copper TSVs and the temperature dependent initial yield stress and hardening coefficients from bow measurements of electroplated thin copper films on silicon under thermal cycling conditions. A FIB trench technique combined with digital image correlation is furthermore used to capture the residual stress state on the surface of TSVs. The extracted properties were discussed and used accordingly to investigate the pumping and protrusion of copper-TSVs during thermal cycling. Furthermore, the cracking and delamination risks caused by the elevated temperature variation during BEoL ILD deposition are investigated with the help of fracture mechanics approaches, in particular.