Stress chip measurements of the internal package stress for process characterization and health monitoring

The experimental observation of the actual thermo-mechanical weak points in microelectronics packages remains a big challenge. Recently, a stress sensing system has been developed by the publicly funded project that allows measuring the magnitudes and the distribution of the stresses induced in the silicon dies by thermo-mechanical loads. The paper reports investigations on industrial QFN packages of 6×6×1mm
³
in size. The stress field has been recorded before and after soldering the component to the PCB as well as during thermal cycle and bending tests. Onset and evolution of internal damages have been detected by changes in the stress at the chip surface due to degradations of materials or interfaces within the course of the thermal cycling test. Applying 3-D x-ray computer tomography, the damages inside the packages have been validated at several stages during the test. All measurements are supplemented by finite element simulations based on calibrated models for in-depth analysis and for extrapolating the stress results to sites of the package that are not measured directly. The methodology of closely combining stress measurements and FE simulation presented in this paper has been able to validate the stress sensing system for tasks of comprehensive design and process characterization as well as for health monitoring. It allows achieving both, a substantial reduction in time-to-market and a high level of reliability under service conditions, as needed for future electronics and smart systems packages.