High speed and area efficient vedic multiplier

High speed pipelined multiplier architecture is proposed in this paper. The pipelined architecture consists of 3 stages. 1
^st
stage consists of the 4 - bit Vedic Multiplication unit. 2
^nd
stage consists of partial products and carry. 3
^rd
stage consists of adders and the result of the multiplication. This paper presents the efficiency of Urdhva Triyagbhyam Vedic method for multiplication which strikes a difference in the actual process of multiplication itself. It enables parallel generation of partial products and eliminates unwanted multiplication steps. The proposed algorithm is modeled using Verilog, a hardware description language. It is found that 11 logic cells are required to build nibble multiplier. The propagation time of the proposed architecture is found to be 4.585ns. Implementation has been done for the Xilinx FPGA device, Spartan-3E. The results shows that multiplier implemented using Vedic multiplication is efficient in terms of area and speed compared to its implementation using Array and Booth multiplier architectures.