Laterally-asymmetric-channel-insulated-shallow-extension-silicon-on-nothing LAC-ISE-SON MOSFET for improved reliability and digital circuit simulation

In the present paper, the application of Laterally Asymmetric Channel Insulated Shallow Extension Silicon On Nothing (LAC-ISE-SON) architecture for analog and digital circuits is analyzed. The LAC-ISE-SON architecture shows improved reliability and hot carrier degradation issues as compared to symmetric channel ISE-SON architecture optimized at the same threshold voltage. The improved analog and digital performance in LAC-ISE-SON as compared to ISE-SON architecture shows the suitability of the device for sub-90nm device regime. We also investigate the effect of L
_HD
variation (highly doped region) on leakage current and other parameters of the device architecture.