A design of multi-core system based on Avalon bus

With the development of a large scale integrated circuit and semiconductor production process, multi-processor on-chip system provides a feasible solution for the highly parallel computation and communications. In this paper, taking JPEG decoding as the starting point, a decoding system with multi-core processors based on the Avalon bus is presented. The paper also introduced the principle of JPEG decoding briefly and the hardware architecture of this system. And we also analyze the parallel process of JPEG decoding. Based on it, to verify the resource comparison, it is compared with the JPEG decoding system based on the AHB bus with 4-core on the EP2S180 FPGA development board. According to the experiments, the JPEG decoding system based on the Avalon bus with multi-core takes up less resource, and compared with the system based on the Avalon BUS with single-core, the total decoding time of the same four pictures of this system saves about 66.7%.