Retargetable multi-level debugging in HW/SW codesign

Debugging is a standard part of an embedded system design process. The debugger is used for a target application debugging and for a testing of the designed system. The target application debugging can be performed either on a statement-accurate level (i.e. source-language level debugging) or on an instruction-accurate level (i.e. assembly-language level debugging). The architecture design debugging is done on a cycle-accurate level. Nowadays embedded systems are often parallel-based. Therefore, it is important to allow debugging of systems with more than one application-specific instruction set processors (ASIP). Since the current trend of ASIP design is focused on automatic tool-chain generation, the debugger must be retargetable to arbitrary architecture. In this paper, we present the concept of an automatically generated multi-level retargetable debugger. This debugger can operate on each of the previously mentioned levels and it allows debugging of multiprocessor systems. The experimental results can be found at the end of the paper.