A 32-core RISC microprocessor with network accelerators, power management and testability features

This paper describes our third generation multicore processor that exhibits a high level of integration [1]. The current design doubles the number of cores, triples the frequency and more than quadruples total memory bandwidth over [1]. It contains 700M transistors and has been fabricated in a 65nm process technology, with 10 layers of copper interconnect and C4 bumps. It contains 32 MIPS cores, 4MB of level 2 cache, multiple hardware accelerator units, 4 72b DDR3 memory controllers operating at 1600 MHz, 20 generic SerDes lanes up to 6.25Gb/s, additional network and boot interfaces and general purpose I/Os. Maximum frequency is 1.6GHz for cores and L2 cache. Excluding I/O, thermal design power ranges from 40W to 65W depending on the frequency bin.