Design of UWB RF receiver front-end with heterogeneous chip integration

In this work, a 3-5 GHz CMOS UWB RF receiver front-end design is described. The design was realized using integrated passive device (IPD) package format as system-in-package (SiP) application. The CMOS circuit consists of a fully differential common gate-low noise amplifier (CG-LNA), an IQ downconversion mixer, and a variable gain amplifier. Three low loss IPD transformer baluns are used to convert unbalanced signals into balanced signals for feeding into the RF and LO input ports of the CMOS circuit. Measurement results indicate that the average conversion gain is 16.3 dB while the average IIP3 and noise figure are around -10.4 dBm and 6.1 dB, respectively, over the entire operating frequency range.