The FPGA implementation of multiplicative inverse value of GF(28) generator using Extended Euclid Algorithm (EEA) method for Advanced Encryption Standard (AES) algorithm

Extended Euclid Algorithm (EEA) is one of the alternatives in gaining the multiplicative inverse value in finite field GF(2
⁸
). Previously, the look-up table (LUT) approach is widely used for this purpose, especially in hardware cryptographic implementations. In this paper, the EEA method is used to build the multiplicative inverse value generator as an alternative of the commonly used LUT method. The generator is implemented in hardware environment using Verilog HDL. By the aid of Altera QuartusII, the generator design is synthesized with the total of 9,940 logic gates and 5,957 instances, with the propagation delay of 7.63 ns. As a proof of hardware implementation, the design is downloaded into an Altera EPF10K70RC240-4 FPGA. This EEA-based inverse generator is proposed to create an alternative approach in generating the inverse value in Advanced Encryption Standard (AES) for hardware-based implementation.