On bit sequential multipliers

Recently bit sequential multiplier algorithms have been found more useful in the area of interconnection of multiple processors within a VLSI structure [1], [2]. The object of the present paper is to suggest modified bit sequential algorithms to achieve more speed and to attain its conformity with other algorithms such as division, square-rooting etc. with a view to utilize them in future arithmatic arrays. In the present paper the following has been taken up: a) Bit sequential multiplier using carry look-ahead technique, b) Bit sequential multiplier using most significant bit first, and c) Negabinary bit sequential multiplier