A single-chip decoder for the POCSAG radiopaging code

An integrated low power consumption POCSAG (Post Office Code Standardization Advisory Group) decoder and pager controller circuit is described, and some information on the SAC-MOS (self-aligned contact CMOS) process used to manufacture it is given. The decoder implements digital filtering, clock recovery, synchronization, error detection and correction, and user interface functions. Since this IC has nonvolatile user address memory (EEPROM) on chip, only two integrated circuits are required to build a complete miniature alert-only pager. The characteristics of the decoder are summarized, and application examples are shown.<
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