Optimized design of hybrid CMOS and CNFET 32 nm dual-X current conveyor

There is a rapid need to explore circuit designs in the newly emerging technologies to help extend the saturating Moore's Law. This paper presents the optimized design and performance analysis of Dual-X Current Conveyor with the Hybrid CMOS and CNFET technologies at 32nm technology node. Current Bandwidth, Input and Output Port resistances of the device and the average power dissipated are chosen as the parameters of reference for carrying out the analysis. Simulations have been carried out using HSPICE simulator at a reduced power supply of ±0.9V.