Fin-Height Effect on Poly-Si/PVD-TiN Stacked-Gate FinFET Performance

We compared the electrical characteristics, including mobility and on -state current
I
_on
, of n
⁺
-poly-Si/PVD-TiN stacked-gate FinFETs with different fin heights
H
_fin
. The mobility was enhanced in devices with taller fins due to increased tensile stress. However, as gate length
Lg
decreases,
I
_on
for devices with tall fins becomes worse, probably due to a high parasitic resistance
Rp
. Furthermore,
V
_th
variation increased with increasing
H
_fin
due to rough etching of the fin sidewall. Process technologies for reducing
Rp
and etching technology that yields smooth precise profiles are essential to exploit the high performance of tall FinFETs.