Time-interleaved single-slope ADC using counter-based time-to-digital converter

In this paper, a time-domain analog-to-digital converter (ADC) using time-to-digital converter (TDC) is presented. The use of TDC in ADCs is a promising technique for future scaled CMOS processes, as it relies on time-resolution rather than voltage resolution. In the proposed ADC, a single-slope capacitor-discharge method is employed to convert input voltage into time, which relaxes the time-domain linearity requirement of comparator. In addition, time-interleaving is employed to increase the time resolution. Lastly, a shared counter-based TDC is used for compact and simple time quantization. Simulation results in 0.25μm CMOS shows the feasibility of the proposed architecture.