An Improved F-M Partitioning Algorithm in Parallel Logic Simulation

The increasing complexity of digital VLSI designs is causing the simulation execution time to increase enormously. Circuit partitioning is an efficient way to speed up the parallel simulation and reduce the communication overhead. Based on classical F-M heuristic algorithm, we proposed a multilevel partitioning approach TCFM, which can get fast convergence of F-M algorithm by refining the initial partitioning. The simulator was implemented on Network of workstations and a benchmark of ISCAS85 was executed to show that it is feasible to obtain the speedup and lower communication overhead.