Fast extraction of extrinsic cells in a NVM array after retention under gate stress

As NVM technology gains maturity, new application fields emerge, often implying new product requirements, especially at high temperature. The data retention is a key criterion for good reliability cells. Many previous studies have already dealt with the charge leakage but some of them seem to show a leakage through SiO
₂
tunnel oxide [1] while others seem to show a leakage through ONO [2]. We have already proposed an experimental way to identify the involved paths by biasing the cell during data retention [3]. The applied bias is used to cancel either the electric field across tunnel oxide or across ONO, depending on the sign of this bias.