A framework for verifying functional correctness in Odin II

FPGA architecture exploration is a topic of great interest to hardware researchers. By synthesizing many hardware descriptions with different architecture specifications, it is possible to compare the generated circuits and draw a conclusion about those specifications. In order to be confident in results obtained from this exploration, it is necessary to verify that the circuits have been compiled correctly. In this paper, we outline the simulator implemented in the VTR CAD tool flow. We detail the features of the simulator and cover its value to researchers performing architecture exploration.