A power-efficient integrated input/output completion detection circuit for asynchronous-logic quasi-delay-insensitive Pre-Charged Half-Buffer

We propose a power- and area-efficient completion detection circuit for improved asynchronous-logic (async) quasi-delay-insensitive (QDI) Pre-Charged Half-Buffer (PCHB) handshake communications. These improved attributes can be achieved by integrating the (separate) input and output completion detection circuits (within the async QDI PCHB circuit) into an integrated input/output completion detection circuit in the transistor level, hereby reducing leakage current paths (leakage power dissipation) and circuit overheads. Moreover, by integrating a reset signal into the integrated input/output completion detection circuit, a stable output state can be achieved during the initialization stage. Based on the simulations on 4×4-bit pipeline multipliers (@1V, 65nm CMOS process), we show that the multiplier with our proposed approach is 37% lower power dissipation (@400MHz input rate), yet 39% lower energy dissipation (per-operation), 35% lower energy-delay product and 21% lesser number of transistors (compared to a conventional design with separate input and output completion detection circuits). These improved results are achieved with an insignificant cost of 5% longer delay (slower speed).