Low-power, low-offset stacked analog latch using an offset cancellation technique

In this paper, a low-power, low-offset analog latch is proposed. A stacked analog latch and a novel offset cancellation technique were combined to achieve low-power and low-offset analog latch. Circuit simulations demonstrated that power dissipation could be reduced by 35% in comparison with using a conventional offset cancellation technique. A test chip fabricated by using 180-nm CMOS technology showed that the proposed circuit reduced the standard deviation of the offset voltage from 15.5 to 3.3 mV. Moreover, the proposed circuit could maintain offset low in the range of the input common level from 0.6 to 1.6 V.