A high-performance configurable VLSI architecture for integer motion estimation in H.264

A high-performance configurable integer motion estimation VLSI architecture based on parallelogram data matching pattern for H.264 is proposed in this paper. Through rational design for the data flow and processing module array, the memory traffic is reduced; data reusability in vertical direction is improved. Furthermore, the number of processing element is configured according to the area-speed requirement, data reusability in horizontal direction is controlled, and fast matching in large searching window is realized. The design is described with Verilog HDL, and is logic synthesized with Synopsys DC under SMIC 0.13nm process. With 300MHz clock frequency, when the PE number is the configured to 5, the search window size is 65×65, the speed can reach 36 fps, which can meet the speed requirements of real-time high-definition video encoding (1920×1088@30fps).