Advanced channel engineering achieving aggressive reduction of VT variation for ultra-low-power applications

We have achieved aggressive reduction of V
T
variation and V
DD-min
by a sophisticated planar bulk MOSFET named ‘Deeply Depleted Channel ™ (DDC)’. The DDC transistor has been successfully integrated into an existing 65nm CMOS platform by combining layered channel formation and low temperature processing. The 2x reduction of V
T
variation in 65nm-node has been demonstrated by matching SRAM pair transistors, 2x improvement in SRAM static noise margin (SNM) and 300 mV V
DD-min
reduction of 576Kb SRAM macros to 0.425 V using conventional 6T cell layout.