Fault detection and diagnoses methodology for adaptive digitally-calibrated pipelined ADCs

This paper presents a cost-effective methodology for fault detection and diagnosis in the adaptive digitally-calibrated pipelined ADCs. In the proposed method, the analog portions of the design are tested utilizing the digital output codes. The test stimulus is generated on-chip. In contrast with the conventional method where the test is usually done at the end of the calibration process, the proposed method utilizes the uncalibrated output codes of the DUT to generate the code error signature (Cεs), which is the difference between the expected (ideal) and the uncalibrated output codes. Interpreting (Cεs), the process of fault isolation and fault value assessment can be done. To demonstrate the methodology, a ten-stage digitally-calibrated pipelined ADC is modeled and simulated using MATLAB. Faults having different type and values are intentionally injected in different places of the design. The simulation results show that Cεs of each fault has pattern dependence on the faulty portion, fault type and fault value. Therefore, the faulty (or even the weak) portion(s) of the DUT can be identified, which is useful for enhancing the reliability of the subsequent design generation.