A 1.3mW CMOS 65nm 4th order 52dB-DR continuous-time analog filter for DVB-T receivers

In this paper a 8.2MHz-f
_@-3dB
bandwidth Filter-&-Amplifier to be embedded in a DVB-T RX chain is presented. The filter has been integrated in 65nm CMOS node, working with a V
_DD
/V
_TH
ratio (supply/threshold voltage) as low as 2. Operating point issues due to low V
_DD
/V
_TH
ratio has been resolved by a proper bias circuit. Since such bias circuit is part of the filter circuit, its impact on filter performance have been studied and considered in the design. Power consumption is minimized by using a novel algorithm based on Matlab procedure, which guarantees the minimum power consumption for a given transfer function, noise and linearity requirements. The device consumes 1.3mW from a single 1.2V supply voltage, features -10dBm-IIP3 at 32dB pass-band Gain, and 1.6mV
_rms
output integrated noise over the pass-band (300kHz÷8.2MHz).