Analysis of the New Latchup Model for Deep Sub-micron Integrated Circuits

The paper simulated the SEL happening process of the CMOS inverter fabricated the 0.18um technology. The results show that the intrinsic parasitic lateral NPN (QN) and PNP (QP) transistor of the NMOS and PMOS in the CMOS inverter, which could result in the changes of the voltage and the current of the drain when the SEL happening, can delay latch up occurring time and reduce the latch up current. The origin model was improved based on the simulated results. The result studying the improved latch up model shows that the smaller ratios of the internal parasitic resistors between R
_W1
and R
_W2
or R
_S1
and R
_S2
could lead to smaller latch up current and delay more time for the latch up occurrence.