Mixed-Signal VLSI Design in 0.5µm Process of Nano-Power Subcompact Mirror-Amplifier for AccuSensor

Emerging semiconductor VLSI requires improved device density on a single chip solution that many parameters are becoming vital concern for cost reduction by lowering the chip area, lowering power dissipation, reducing operating voltage, increasing speed etc. A previously designed precision sensor application mirror-amplifier was considered for optimizing in chip area consumption and improves sensing to make it ultra-precise, also this work has reduced the IC to a subcompact die sizes. MAGIC is used as two-dimensional CAD layout tool. Also PSPICE is used for electrical simulation purposes employed by extraction tool. Feature size is taken from mSCN3M_SUBM.30 process for 0.6μm layout and 0.5μm enhanced fabrication process. The improved design has area of 101λ×48λ (minimized from 126λ×59λ) or 30.3μm×15μm (minimized from 37.8μm×17.7μm) in 0.6μm CMOS design process. For multi-die placement, two sets of chip are designed those are placed on the four sub-dies in a single MOSIS tiny chip die. For one set of chip coincidence detector is designed to make the mirror-amplifier ultra precise, buffer stage is designed for another set of chip to drive large load. This paper presents details of the key research works, results, completed chip layout and packaging of the chip.