Effects of Gate Oxide and Junction Nonuniformity on the DC and Low-Frequency Noise Performance of Four-Gate Transistors

The effects of imperfections on the electrical performance of four-gate field-effect transistors (G4-FETs) have been studied. Variations in the oxide trap distribution and in the metallurgical boundary of the junction gates impact the low-frequency noise and the static (dc) performance of the G4-FET. By modeling, iterative characterization of published experimental data, and extensive simulations, it is shown that these effects originate from trap distributions in the gate oxides and in the depleted regions of the semiconductor channel. The proposed models are based on established models, such as the unified flicker noise model, with modifications and improvements that extend to trap distributions with gradients, variable frequency slope
$ \alpha$
of
$\hbox{1}/f^{\alpha}$
noise spectra, and are applicable for gate stacks with high-k dielectrics, such as
$ \hbox{HfO}_{2}$
and HfSiON. The characterization procedures allowed for identifying optimum profiles of the metallurgical boundary of junction gates, which simultaneously improve the dc and noise performances of the G4-FET, such as subthreshold swing and low noise. The results indicate the importance of the precise control of depletion and conduction in the channels of multiple-gate FETs.