A Darlington-Enhanced CMOS Oscillator Architecture

A fully differential CMOS oscillator using Darlington composite pMOS transistors is presented. The composite transistor structure increases gain of the negative-Gm stage for a reliable startup and improves device reliability due to use of high-voltage transistors. To achieve good phase noise available with large voltages and the speed of small active devices in a modern CMOS process, a higher (2.8 V) power supply requiring a combination of low- and high-voltage transistors is used. In addition, the oscillator uses negative feedback to reduce amplitude variation due to
$LC$
-tank loading. Circuit functionality is confirmed with a test circuit fabricated in a standard 130-nm CMOS process. The oscillator reaches a phase noise better than
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121.2 dBc/Hz at 1-MHz offset across a tuning range of 3015 to 5298 MHz while consuming a less than 10.6-mA current from a 2.8-V power supply.