Designing on-wafer calibration standards for advanced high-speed BiCMOS technology

This work presents design methodology of on-wafer calibration standards covering frequencies up to 110 GHz and optimized for the BiCMOS processes. We discuss such topics as layout optimization of distributed and lumped standards, measurement and verification of electrical characteristics along with the definition of the on-wafer calibration reference impedance and measurement reference plane. Also, we present calibration verification results and some characteristics of an active DUT implemented in Si/SiGe:C ST Microelectronics' BiCMOS9MW process technology.