LVDS driver design for high speed serial link in 0.13um CMOS technology

This paper presents a LVDS (low voltage differential signal) driver, which works at 2 Gbps, with a pre-emphasis circuit compensating the attenuation of limited bandwidth of channel. To make the output common-mode (CM) voltage stable over process, temperature, and supply voltage variations, a closed-loop negative feedback circuit is added in this work. The LVDS driver is designed in 0.13 um CMOS technology using both thick (3.3 V) and thin (1.2 V) gate oxide device, simulated with transmission line model and package parasitic model. The simulated results show that this driver can operate up to 2 Gbps with random data patterns.