An architecture independent test methodology for SRAM FPGAs

The effective utilization of FPGAs in the implementation of reconfigurable circuits is contingent on the logic and routing integrity of the devices. To assure this integrity, a means of detecting and localizing logic and routing resource faults is required. This paper presents an architecture independent methodology for testing logic and routing resources of SRAM FPGAs. The proposed methodology employs a functional level device model for the implementation of architecture independent algorithms that allow dynamic generation of test configurations. The flexible device model allows integration of logic and routing resource testing while enhancing the applicability of the test methodology to a broad range of device architectures and sizes.