Design of low-power quaternary flip-flop based on dynamic source-coupled logic

A novel quaternary D-flip-flop is proposed by using dynamic source-coupled logic (SCL) for high performance processing element in VLSI system. Its key components, the threshold detectors, are based on differential-pair circuit (DPC). The combination of multiple-valued source-coupled logic and differential-pair circuit makes it low power and more compact. The performance is evaluated by HSPICE simulation with 0.18μm CMOS technology. The power dissipation, transistor numbers and delay are reduced to 71 percent, 90 percent and 84 percent respectively in comparison with a corresponding CMOS implementation.