A 95dB SNDR audio ΔΣ modulator in 65nm CMOS

A discrete time single loop 3rd order 5-bit ΔΣ modulator is implemented in general purpose 65nm CMOS. A passive capacitor analog summing method without signal attenuation is developed and combined with an asynchronous self-timing successive approximation quantizer. The modulator achieves 95dB SNDR in audio bandwidth and consumes only 371µW from 1V supply. Under 0.6V supply, the SNDR performance keeps at 90.2dB with 133µW power dissipation. The active core area is 0.41mm
²
.