A time-domain latch interpolation technique for low power flash ADCs

A Time-domain latch interpolation technique is presented for low power flash analog-to-digital converter (ADC). The proposed technique reduces the number of first stage latches by half, and thus, reduce power consumption and hardware complexity. A prototype 6bit 1GS/s flash ADC was designed for concept proof in a 90nm CMOS process. The first stage comparators are calibrated by adjusting body voltages. The ADC core consumes 24mW at 1.2V supply. The measured INL and DNL are 0.55LSB and 0.6LSB, respectively after calibration. The SNDR and SFDR are 32.56dB and 43.53dB at 1GS/s with a 50MHz input.