Technology scaling effects on the ESD performance of silicide-blocked PMOSFET devices in nanometer bulk CMOS technologies

We present technology scaling effects on the ESD performance of silicide-blocked PMOSFET devices. Stress elements and their effects are characterized using TLP and analyzed with the help of TCAD. Stress liners show no significant effect on ESD performance, whereas the source/drain eSiGe reduces on-resistance by up to 20% and failure current by up to 14%.