Analog CMOS processor for early vision processing with highly reduced power consumption

A new approach to an analog ultra-low power vision chip design is presented. The prototype chip performs low-level convolutional image processing algorithms in real time. The circuit is implemented in 0.35 µm CMOS technology, contains 64 × 64 SIMD matrix with embedded analogue processors APE (Analogue Processing Element). The photo-sensitive-matrix is of 2.2 µm × 2.2 µm size, giving the density of 877 processors per mm2. The matrix dissipates less than 0.4 mW (less than 0.1 µW per processor) of power under 3.3 V supply, and their image processing speed is up to 100 frames/s.