Design of a novel adaptive FIR filter based on FPGA

In this paper, the design of adaptive FIR digital filter is studied and a novel implementations of adaptive FIR filter based on multiplier-free structure is proposed. The implementation scheme based on the distributed algorithm uses access to a range of look-up table(LUT) to replace the traditional method of multiply-accumulate operations. The update of the adaptive filter weights is based on the quantization error least mean square algorithm(QE-LMS). To reduce the time, the update process of the LUT which stored filter weights is realized by a novel LUT update using a matched auxiliary LUT. The filter is described with VHDL, and realized on Cyclone series chip. The system simulation and timing analysis show that the proposed method can implement FIR filters with the smaller resource usage and higher speed.