Analysis of power supply noise mitigation circuits

Power supply noise has become an increasing concern for circuit designers with the recent advances in technology. As a result there has been an introduction of active supply noise mitigation circuits in addition to the currently used passive bypass/decoupling capacitors for on-chip noise suppression. This paper proposes figures of merit for characterizing the various emerging mitigation circuits as well as provides a theoretical and practical analysis of a switched capacitor based active mitigation technique for the CMOS 65 nm technology node.