Flexible simulation and modeling for 2D topology NoC system design

Network on Chip (NoC) is a new paradigm that can solve the problems related to System on Chip (SoC) design. These problems and challenges become more significant when the complexity of SoC increases. The vast volume of these challenges requires a new and flexible NoC test framework (simulator) to be investigated. We have developed a general purpose SystemC based NoC simulator that employs some new approaches to have a superior test system as compared to the past NoC simulators. The simulator mainly target 2D regular NoC topologies where deterministic and adaptive routing techniques that play a key role in the NoC performance. Various NoC design parameters are analyzed by trading off throughputs and latencies. The results show that for some cases the new Line-Probe routing is faster and contention free for local traffic in Torus topology.