Comparison of binary and LFSR counters and efficient LFSR decoding algorithm

This paper provides a direct comparison between a fast binary counter, built using a hierarchical Manchester carry chain, and a counter built using a linear feedback shift register (LFSR). The comparison is focused on speed, power and area consumption. We demonstrate the use of LFSRs as an alternative to conventional binary event counters. In order to use an LFSR as a counter, we developed an efficient algorithm for decoding the pseudo-random bit patterns of the LFSR counter to a known binary count. We implement 4-bit, 8-bit, 16-bit and 32-bit LFSR and binary counters in a 0.5-μm CMOS process. The hypotheses that LFSR counters leads to reduced area and higher speed were validated using simulation and measurement results.