A fast synthesizer using a bang-bang frequency comparator and locking status indicator

Frequency synthesizer is one of the most challenging blocks in wireless transceivers which works as a local oscillator in both receiver and transmitter blocks. It is generally based on charge pump based phase-locked loops structure. This paper describes the new application of fast charge pump based PLL architecture. The PLL uses a bang-bang frequency comparator (BBFC) as well as a locking status indicator (LSI) in the synthesizer. BBFC is a circuit that can detect frequency regardless to the phase error and LSI detect the locking status in order to change the charge pump current. BBFC along with the LSI works as a lock-aid circuit that can be used to speed up the frequency acquisition process, without affecting the subsequent phase acquisition and hence improves the transient behaviour of the system. Simulations in MATLAB show that the proposed architecture has more proper settling time than the standard CPPLL. Here the settling time is about 60% lower with respect to a standard CPPLL topology where these two have the same element and the same output frequency range. The simulations have performed for WiMAX (Worldwide Interoperability for Mobile Access) applications. The input frequency has been chosen equal to 20 MHz and output Frequency covers the mobile WiMAX frequency range from 2.3GHz to 2.7 GHz. The division rate changes from 64 to 127 and a second order filter has been implemented in the synthesizer loop.