Frequency switching analysis of an iUPQC with hardware-in-the-loop development tool

This paper presents a frequency switching analysis of an interchanging topology of the Unified Power Quality Conditioner (iUPQC). It includes simulations with hardware-in-the-loop development tool, which allows the control code development (embedded in an actual fixed-point DSP) directly working in a simulated iUPQC (PSCAD/EMTDC simulator). The aim is to reduce the frequency switching of both series and shunt compensators, thus allowing the power rating increase of the converter with the same harmonic mitigation performance. Experimental results are provided for 10 kHz and 3 kHz frequency switching operation.